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1/53 AN1762 application note december 2003 1 introduction the l6205, l6206, l6207 are highly integrated, mixed-signal power ics that allow the user to easily design a control system for two-phase bipolar stepper motors, multiple dc motors and a wide range of inductive loads. figure 1 to figure 3 show the l6205, l6206, l6207 block diagrams. each ic integrates eight power dmos plus other added features for safe operation and flexibility. the l6207 also features a constant t off pwm current control technique ( synchronous mode ) for each of the two full bridges. figure 1. l6205 block diagram. d99in1091a gate logic over current detection over current detection gate logic vcp vboot en a in1 a in2 a en b in1 b in2 b v boot 5v 10v vs a v s b out1 a out2 a out1 b out2 b sense a charge pump voltage regulator thermal protection v boot v boot 10v 10v bridge a bridge b sense b ocd a ocd b by vincenzo marano l6205, l6206, l6207 dual full bridge drivers modern motion control applications need more flexibility that can be addressed only with specialized ic products. the l6205, l6206, l6207 are dual full bridge drivers ics specifically developed to drive a wide range of motors. these ics are one-chip cost effective solutions that include several unique circuit design features. these features allow the devices to be used in many applications including dc and stepper motor driving. the principal aim of this development project was to produce easy to use, fully protected power ics. in addition several key functions such as protection circuit and pwm current control drastically reduce exter- nal components count to meet requirements for many different applications.
AN1762 application note 2/53 figure 2. l6206 block diagram. figure 3. l6207 block diagram. d99in1088a gate logic over current detection over current detection gate logic vcp vboot en a in1 a in2 a en b in1 b in2 b v boot 5v 10v vs a v s b out1 a out2 a out1 b out2 b sense a charge pump voltage regulator thermal protection v boot v boot 10v 10v bridge a bridge b sense b progcl b ocd b ocd a progcl a ocd a ocd b d99in1085a gate logic ocd a ocd b over current detection over current detection gate logic vcp vboot en a in1 a in2 a en b in1 b in2 b vref a v boot 5v 10v vs a v s b out1 a out2 a out1 b out2 b sense a charge pump voltage regulator one shot monostable masking time thermal protection v boot v boot 10v 10v bridge a sense comparator bridge b rc a + - sense b vref b rc b pwm
3/53 AN1762 application note table of contents 1 introduction.................................................................................................................. ..............1 2 main differences between l6205, l6206, l6207 ..................................................................4 3 designing an application with l6205, l6206, l6207 ...........................................................4 3.1 current ratings ............................................................................................................. ...........4 3.2 voltage ratings and operating range ....................................................................................4 3.3 choosing the bulk capacitor................................................................................................. ...6 3.4 layout considerations ....................................................................................................... ......7 3.5 sensing resistors ........................................................................................................... .........9 3.6 charge pump external components .......................................................................................10 3.7 sharing the charge pump circuitry .......................................................................................11 3.8 reference voltage for pwm current control (l6207 only).................................................12 3.9 input logic pins ............................................................................................................ ..........13 3.10 en pins.................................................................................................................... ...............13 3.11 programmable off-time monostable (l6207 only)..............................................................14 3.11.1 off-time selection and minimum on-time (l6207 only) ................................................16 3.11.2 slow decay mode (l6207 only) ...................................................................................17 3.12 over current protection ................................................................................................... .....18 3.13 adjusting the over current detection trip point (l6206 only) ............................................21 3.14 paralleling two full bridges.............................................................................................. .....23 3.14.1 paralleling two full bridges to get a single full bridge ....................................................23 3.14.2 paralleling the four half bridges to get a single half bridge.............................................26 3.15 power management .......................................................................................................... ....27 3.15.1 maximum output current vs. selectable devices..............................................................27 3.15.2 power dissipation formulae for different sequences ......................................................28 4 application example (l 6207) ..................................................................................................32 4.1 decay mode, sensing resistors and reference voltage. .........................................................32 5 appendix - evaluation boards .............................................................................................33 5.1 practispin.................................................................................................................. ............33 5.2 eval6205n ................................................................................................................... ........34 5.2.1 important notes........................................................................................................... .....35 5.3 eval6206n ................................................................................................................... ........39 5.3.1 important notes........................................................................................................... .....40 5.4 eval6206pd .................................................................................................................. .......44 5.4.1 important notes........................................................................................................... .....45 5.5 eval6207n ................................................................................................................... ........49 5.5.1 important notes........................................................................................................... .....50 6 references.................................................................................................................... .............53
AN1762 application note 4/53 2 main differences between l6205, l6206, l6207 l6205, l6206 and l6207 are dmos dual full bridge ics. l6205 (see figure 1) includes logic for cmos/ttl interface, a charge pump that provide auxiliary voltage to drive the high-side dmos, non dissipative over current protection circuitry on the high-side dmos, with fixed trip point set at 5.6 a (see over current protection section), over temperature protection, under voltage lock- out for reliable start-up. in addition, l6206 gives the possibility of adjusting the trip point of the over current protection for each of the two full-bridges (through two external resistors), and its internal open-drain mosfets (see over current protec- tion section) are not internally connected to en pins but to separate ocd pins, allowing easier external diagnos- tics and overcurrent management. l6207 has over current protection function with fixed trip point set at 5.6 a and internal open-drain mosfets connected to en pins, as the l6205, but it also integrates two pwm current controller for each of the two full- bridges (see programmable off-time monostable section). 3 designing an application with l6205, l6206, l6207 3.1 current ratings with mosfet (dmos) devices, unlike bipolar transistors, current under short circuit conditions is, at first ap- proximation, limited by the r ds(on) of the dmos themselves and could reach very high values. l6205, l6206, l6207 out pins and the two v sa and v sb pins are rated for a maximum of 2.8a r.m.s. and 5.6a peak (typical values), corresponding to a total (for the whole ic) 5.6a rms (11.2a peak). these values are meant to avoid damaging metal structures, including the metallization on the die and bond wires. in practical applications, though, maximum allowable current is less than these values, due to power dissipation limits ( see power management section ). the devices have a built-in over current detection (ocd) that provides protection against short circuits between the outputs and between an output and ground ( see over current protection section ). 3.2 voltage ratings and operating range the l6205, l6206, l6207 requires a single supply voltage (v s ), for the motor supply. internal voltage regulators provide the 5v and 10v required for the internal circuitry. the operating range for v s is 8 to 52v. to prevent working into undesirable low supply voltage an under voltage lock out ( uvlo ) circuit shuts down the device when supply voltage falls below 6v; to resume normal operating conditions, v s must then exceed 7v. the hys- teresis is provided to avoid false intervention of the uvlo function during fast v s ringings. it should be noted, however, that dmos's r ds(on) is a function of the v s supply voltage. actually, when v s is less than 10v, r ds(on) is adversely affected, and this is particularly true for the high side dmos that are driven from v boot supply. this supply is obtained through a charge pump from the internal 10v supply, which will tend to reduce its output voltage when v s goes below 10v. figure 4 shows the supply voltage of the high side gate drivers (v boot - v s ) versus the supply voltage (v s ).
5/53 AN1762 application note figure 4. high side gate drivers supply voltage versus supply voltage. note that v s must be connected to both v sa and v sb since the bootstrap voltage (at v boot pin) is the same for the two h-bridges. the integrated dmos have a rated drain-source breakdown voltage of 60v. however v s should be kept below 52v, since in normal working conditions the dmos see a v ds voltage that will exceed v s supply. in particular, during a phase change (when each output of the same h-bridge switches from v s to gnd or vice versa, for example to reverse the current in the load) at the beginning of the dead-time (when all the dmos are off) the sense pin sees a negative spike due to a not negligible parasitic inductance of the pcb path from the pin to gnd. this spike is followed by a stable negative voltage due to the drop on r sense . one of the two out pins of the bridge sees a similar behavior, but with a slightly larger voltage due to the forward recovery time of the integrated freewheeling diode and the forward voltage drop across it (see figure 5). typical duration of this spike is 30ns. at the same time, the other out pin of the same bridge sees a voltage above v s , due to the pcb inductance and voltage drop across the high-side (integrated) freewheeling diode, as the current reverses direction and flows into the bulk capacitor. it turns out that the highest differential voltage can be ob- served between the two out pins of the same bridge, during the dead-time at a phase change, and this must always be kept below 60v [3]. figure 5. currents and voltages during the dead time at a phase change. v s [v] v boot - v s [v] 6 6.4 6.8 7.2 7.6 8 8 8.5 9 9.5 10 10.5 v s sense out 1 out 2 r sense *i r sense *i+v f(diode) pcb parasitic inductance pcb parasitic inductance bulk capacitor equivalent circuit esr esl r sense v s +v f(diode) dangerous high differential voltage
AN1762 application note 6/53 figure 6 shows the voltage waveforms at the two out pins referring to a possible practical situation, with a peak output current of 2.8a, v s = 52v, r sense = 0.33 w , t j = 25c (approximately) and a good pcb layout. below ground spike amplitude is -2.65v for one output; the other out pin is at about 57v. in these conditions, total differential voltage reaches almost 60v, which is the absolute maximum rating for the dmos. keeping differen- tial voltage between two output pins belonging to the same full bridge within rated values is a must that can be accomplished with proper selection of bulk capacitor value and equivalent series resistance (esr), accord- ing to current peaks and chopping style and adopting good layout practices to minimize pcb parasitic induc- tances (see below) [3]. figure 6. voltage at the two outputs during the dead time at a phase change. 3.3 choosing the bulk capacitor since the bulk capacitor, placed between v s and gnd pins, is charged and discharged during ic operation, its ac current capability must be greater than the r.m.s. value of the charge/discharge current. in the case of a pwm current regulation, the current flows from the capacitor to the ic during the on-time (t on ) and from the ic (implementing a fast decay current recirculation technique) or from the power supply (implementing a slow de- cay current recirculation technique) to the capacitor during the off-time (t off ). the r.m.s. value of the current flowing into the bulk capacitor depends on peak output current, output current ripple, switching frequency, duty- cycle and chopping style. it also depends on power supply characteristics. a power supply with poor high fre- quency performances (or long, inductive connections to the ic) will cause the bulk capacitor to be recharged slowly: the higher the current control switching frequency, the higher the current ripple in the capacitor; r.m.s. current in the capacitor, however, does not exceed the r.m.s. output current. bulk capacitor value ( c ) and the esr determine the amount of voltage ripple on the capacitor itself and on the ic. in slow decay, neglecting the dead-time and output current ripple, and assuming that during the on-time the capacitor is not recharged by the power supply, the voltage at the end of the on-time is: , so the supply voltage ripple is: , out 2 out 1 v s i out C esr t on c --------- + ?? ?? i out esr t on c --------- + ?? ??
7/53 AN1762 application note where i out is the output current. with fast decay, instead, recirculating current recharges the capacitor, causing the supply voltage to exceed the nominal voltage. this can be very dangerous if the nominal supply voltage is close to the maximum recommended supply voltage (52v). in fast decay the supply voltage ripple is about: , always assuming that the power supply does not recharge the capacitor, and neglecting the output current ripple and the dead-time. usually (if c > 100 f) the capacitance role is much less than the esr, then supply voltage ripple can be estimated as: i out esr in slow decay 2 i out esr in fast decay for example, if a maximum ripple of 500mv is allowed and i out = 2a, the capacitor esr should be lower than: in slow decay, and in fast decay. actually, current sunk by v sa and v sb pins of the device is subject to higher peaks due to reverse recovery charge of internal freewheeling diodes. duration of these peaks is, tough, very short, and can be filtered using a small value (100200 nf), good quality ceramic capacitor, connected as close as possible to the v sa , v sb and gnd pins of the ic. bulk capacitor will be chosen with maximum operating voltage 25% greater than the maximum supply voltage, considering also power supply tolerances. for example, with a 48v nominal power supply, with 5% tolerance, maximum voltage is 50.4v, then operating voltage for the capacitor should be at least 63v. 3.4 layout considerations working with devices that combine high power switches and control logic in the same ic, careful attention has to be paid to the pcb layout. in extreme cases, power dmos commutation can induce noises that could cause improper operation in the logic section of the device. noise can be radiated by high dv/dt nodes or high di/dt paths, or conducted through gnd or supply connections. logic connections, especially high-impedance nodes (actually all logic inputs, see further), must be kept far from switching nodes and paths. with the l6205, l6206, l6207, in particular, external components for the charge pump circuitry should be connected together through short paths, since these components are subject to voltage and current switching at relatively high frequency (600khz). primary mean in minimizing conducted noise is working on a good gnd layout (see figure 7). i out 2 esr t on t off + c --------------------------- - + ?? ?? esr 0.5v 2a ------------ < 250m w = esr 1 2 -- - 0.5v 2a ------------ < 125m w =
AN1762 application note 8/53 figure 7. typical application and layout suggestions. high current gnd tracks (i.e. the tracks connected to the sensing resistors) must be connected directly to the negative terminal of the bulk capacitor. a good quality, high-frequency bypass capacitor is also required (typi- cally a 100nf200nf ceramic would suffice), since electrolytic capacitors show a poor high frequency perfor- mance. both bulk electrolytic and high frequency bypass capacitors have to be connected with short tracks to v sa , v sb and gnd. on the l6205, l6206, l6207 gnd pins are the logic gnd, since only the quiescent current flows through them. logic gnd and power gnd should be connected together in a single point , the bulk ca- pacitor, to keep noise in the power gnd from affecting logic gnd. specific care should be paid layouting the path from the sense pins through the sensing resistors to the negative terminal of the bulk capacitor (power ground). these tracks must be as short as possible in order to minimize parasitic inductances that can cause dangerous voltage spikes on sense and out pins (see the voltage ratings and operating range section); for the same reason the capacitors on v sa , v sb and gnd should be very close to the gnd and supply pins. refer to the sensing resistors section for information on selecting the sense resistors. traces that connect to v sa , v sb , sense a , sense b , and the four out pins must be designed with adequate width, since high currents are flowing through these traces, and layer changes should be avoided. should a layer change prove neces- sary, multiple and large via holes have to be used. a wide gnd copper area can be used to improve power dissipation for the device. figure 8 shows two typical situations that must be avoided. an important consideration about the location of the bulk capacitors is the ability to absorb the inductive energy from the load, without allowing the supply voltage to exceed the maximum rating. the diode shown in figure 8 prevents the recirculation current from reaching the capacitors and will result in a high voltage on the ic pins that can destroy the device. having a switch or a power connection that can disconnect the capacitors from the ic, while there is still current in the motor, will also result in a high voltage transient since there is no capacitance to absorb the recirculation current. + - v s = 8 52 v gnd gnd gnd gnd sense a sense b v sa v sb v boot cp out 1b out 2b out 1a out 2a d1 d2 r1 rs1 rs2 c3 c4 c1 c2 l6205, l6206, l6207 motors or other loads logic gnd
9/53 AN1762 application note figure 8. two situations that must be avoided. 3.5 sensing resistors each motor winding current is flowing through the corresponding sensing resistor, causing a voltage drop that can be used, by the logic (integrated in the l6207; an external logic can be used with l6205 and l6206), to control the peak value of the load current. two issues must be taken into account when choosing the r sense value: C the sensing resistor dissipates energy and provides dangerous negative voltages on the sense pin during the current recirculation. for this reason the resistance of this component should be kept low. C the voltage drop across r sense is compared with a reference voltage (on v ref pin) by the internal com- parator (l6207 only). the lower is the r sense value, the higher is the peak current error due to noise on vref pin and to the input offset of the current sense comparator: too small values of r sense must be avoided. a good compromise is calculating the sensing resistor value so that the voltage drop, corresponding to the peak current in the load (i peak ), is about 0.5 v: r sense = 0.5 v / i peak . it should be clear that sensing resistor must absolutely be non-inductive type in order to avoid dangerous neg- ative spikes on sense pins. wire-wounded resistors cannot be used here, while metallic film resistors are rec- ommended for their high peak current capability and low inductance. for the same reason the connections between the sense pins, c6, c7, v sa , v sb and gnd pins (see figure 7) must be taken as short as possible (see also the layout considerations section). the average power dissipated by the sensing resistor is: fast decay recirculation: p r ? i rms 2 r sense slow decay recirculation: p r ? i rms 2 r sense d, d is the duty-cycle of the pwm current control, i rms is the r.m.s. value of the load current. gnd gnd gnd gnd sense a sense b v sa v sb r5 c7 c6 l6205, l6206, l6207 dont connect the logic gnd here voltage drop due to current in sense path can disturb logic gnd. dont put a diode here! recirculating current cannot flow into the bulk capacitor and causes a high voltage spike that can destroy the ic. + - v s = 8 52 v
AN1762 application note 10/53 nevertheless, sensing resistor power rating should be chosen taking into account the peak value of the dissi- pated power: , where i pk is the peak value of the load current. using multiple resistors in parallel will help obtaining the required power rating with standard resistors, and re- duce the inductance. r sense tolerance reflects on the peak current error: 1% resistors should be preferred. the following table shows r sense recommended values (to have 0.5v drop on it) and power ratings for typical examples of current peak values. 3.6 charge pump external components an internal oscillator, with its output at cp pin, switches from gnd to 10v with a typical frequency of 600khz (see figure 9). figure 9. charge pump. when the oscillator output is at ground, c 5 is charged by v s through d 2 . when it rises to 10v, d 2 is reverse biased and the charge flows from c 5 to c 8 through d 1 , so the v boot pin, after a few cycles, reaches the max- imum voltage of v s + 10v - v d1 - v d2 , which supplies the high-side gate drivers. with a differential voltage between v s and v boot of about 9v and both the bridges switching at 50khz, the typ- ical current drawn by the v boot pin is 1.85 ma. i pk r sense value [ w ] r sense power rating [w] alternatives 0.5 1 0.25 1 0.5 0.5 2 x 1 w , 0.25w paralleled 1.5 0.33 0.75 3 x 1 w , 0.25w paralleled 2 0.25 1 4 x 1 w , 0.25w paralleled p r i pk 2 r sense ? l6205, l6206, l6207 v s + 10 v - v d1 v s - v d1 f = 600 khz v sa v sb v boot cp d1 d2 r4 c8 c5 r ds(on) = 70 w 10 v 10 v 5 v r ds(on) = 70 w to high-side gate drivers 10 v f = 600 khz charge pump oscillator v s + 10 v - v d1 - v d2
11/53 AN1762 application note resistor r4 is added to reduce the maximum current in the external components and to reduce the slew rate of the rising and falling edges of the voltage at the cp pin, in order to minimize interferences with the rest of the circuit. for the same reason care must be taken in realizing the pcb layout of r4 , c5 , d1 , d2 connections (see also the layout considerations section). recommended values for the charge pump circuitry are: d1, d2 : 1n4148 r4 : 100 w (1/8 w) c5 : 10nf 100v ceramic c8 : 220nf 25v ceramic due to the high charge pump frequency, fast diodes are required. connecting the cold side of the bulk capacitor (c8) to v s instead of gnd the average current in the external diodes during operation is less than 10 ma (with r4 = 100 w ); at startup (when v s is provided to the ic) is less than 200 ma while the reverse voltage is about 10 v in all conditions. 1n4148 diodes withstand about 200 ma dc (1 a peak), and the maximum reverse voltage is 75 v, so they should fit for the majority of applications. 3.7 sharing the charge pump circuitry if more than one device is used in the application, it's possible to use the charge pump from one l6205, l6206 or l6207 to supply the v boot pins of several ics. the unused cp pins on the slaved devices are left uncon- nected, as shown in figure 10. a 100nf capacitor (c8) should be connected to the v boot pin of each device. supply voltage pins (v s ) of the devices sharing the charge pump must be connected together. the higher the number of devices sharing the same charge pump, the lower will be the differential voltage avail- able for gate drive (v boot - v s ), causing a higher r ds(on) for the high side dmos, so higher dissipating power. in this case it's recommended to omit the resistor on the cp pin, obtaining a higher current capability of the charge pump circuitry. better performance can also be obtained using a 33nf capacitor for c5 and using schottky diodes (for example bat47 are recommended). sharing the same charge pump circuitry for more than 34 devices is not recommended, since it will reduce the v boot voltage increasing the high-side mos on-resistance and thus power dissipation. figure 10. sharing the charge pump circuitry. v sa v sb v boo t cp c18 = 100 nf to high-side gate drivers v sa v sb v bo o t c8 = 100nf to high-side gate drivers to ot her devices cp l6205, l6206, l6207 l6205, l6206, l6207 d1 = bat47 d2 = bat47 c5 = 33nf
AN1762 application note 12/53 3.8 reference voltage for pwm current control (l6207 only) the l6207 has two analog inputs, v refa and v refb , connected to the internal sense comparators, to control the peak value of the motor current through the integrated pwm circuitry. in typical applications these pins are con- nected together, in order to obtain the same current in the two motor windings. a fixed reference voltage can be easily obtained through a resistive divider from an available 5 v voltage rail (maybe the one supplying the c or the rest of the application) and gnd. a very simple way to obtain a variable voltage without using a dac is to low-pass filter a pwm output of a c (see figure 11). assuming that the pwm output swings from 0 to 5v, the resulting voltage will be: where d c is the duty-cycle of the pwm output of the c. assuming that the c output impedance is lower than 1k w, with r lp = 56k w , r div = 15k w , c lp = 10nf and a c pwm switching from 0 to 5v at 100khz, the low pass filter time constant is about 0.12 ms and the remaining ripple on the v ref voltage will be about 20 mv. using higher values for r lp , r div and c lp will reduce the ripple, but the reference voltage will take more time to vary after changing the duty-cycle of the c pwm, and too high values of r lp will also increase the impedance of the v ref net at low frequencies, causing a poor noise immunity. as sensing resistor values are typically kept small, a small noise on v ref input pins might cause a considerable error in the output current. it's then recommended to decouple these pins with ceramic capacitors of some tens of nf, placed very close to v ref and gnd pins. note that v ref pins cannot be left unconnected, while, if connected to gnd, zero current is not guaranteed due to voltage offset in the sense comparator. the best way to cut down (ic) power consumption and clear the load current is pulling down the en pins. with very small reference volt- age, pwm integrated circuitry can loose control of the current due to the minimum allowed duration of t on (see the programmable off-time monostable section). figure 11. obtaining a variable voltage through a pwm output of a c. v ref 5v d m c r div r lp r div + ----------------------------------------- = r lp c lp v ref gnd pwm output of a c r div
13/53 AN1762 application note 3.9 input logic pins in1 a , in2 a , in1 b , in2 b are cmos/ttl compatible logic input pins. the input comparator has been realized with hys- teresis to ensure the required noise immunity. typical values for turn-on and turn-off thresholds are v th,on = 1.8v and v th,off = 1.3v. pins are esd protected (see figure 12) (2kv human-body electro-static discharge), and can be directly connected to the logic outputs of a c; a series resistor is generally not recommended, as it could help inducted noise to disturb the inputs. all logic pins enforce a specific behavior and cannot be left unconnected. figure 12. logic input pins. 3.10 en pins the en a , en b pins are, actually, bi-directional: as an input, with a comparator similar to the other logic input pins (ttl/ cmos with hysteresis), they control the state of the powerdmos. when each of the two pins is at a low logic level, all the powerdmos of the corresponding h-bridge (a or b) are turned off. in l6205 and l6207 the en pins are also connected to the two corresponding open drain outputs of the protection circuits that will pull the pins to gnd if over current in the corresponding h-bridge or over temperature conditions exist. in l6206 the open drain outputs are on separate pins, ocd a and ocd b , allowing easier external diagnostics and overcurrent management. for this reason, with l6205 and l6207 (and l6206 if en pins are connected to diag pins) en pins must be driven through a series resistor of 2.2k w minimum (for 5v logic), to allow the voltage at the pin to be pulled below the turn-off threshold. a capacitor (c en in figure 13) connected between each en pin and gnd is also recommended, to reduce the r.m.s. value of the output current when overcurrent conditions persist (see over current protection section). en pin must not be left unconnected. figure 13. en a and en b input pins. 5v d01in1329 esd protection 5v push-pull output r en c en en a or en b ocd a or ocd b 5v push-pull output r en c en en a or en b en a or en b l6205, l6207 l6206
AN1762 application note 14/53 3.11 programmable off-time monostable (l6207 only) the l6207 includes a constant off time pwm current controller for each of the two bridges. the current control circuit senses the bridge current by sensing the voltage drop across an external sense resistor connected be- tween the source of the two lower power mos transistors and ground, as shown in figure 14. as the current in the load builds up the voltage across the sense resistor increases proportionally. when the voltage drop across the sense resistor becomes greater than the voltage at the reference input (vref a or vref b ) the sense com- parator triggers the monostable switching the low-side mos off. the low-side mos remain off for the time set by the monostable and the motor current recirculates in the upper path. when the monostable times out the bridge will again turn on. since the internal dead time, used to prevent cross conduction in the bridge, delays the turn on of the power mos, the effective off time is the sum of the monostable time plus the dead time. figure 14. pwm current control circuitry (l6207 only). figure 15 shows the typical operating waveforms of the output current, the voltage drop across the sensing re- sistor, the rc pin voltage and the status of the bridge. immediately after the low-side power mos turns on, a high peak current flows through the sensing resistor due to the reverse recovery of the freewheeling diodes. the l6207 provides a 1 s blanking time t blank that inhibits the comparator output so that this current spike cannot prematurely re-trigger the monostable. drivers + dead time s q r drivers + dead time 2h 1h 2l 1l out2 a(or b) sense a(or b) r sense d02in1352 rc a(or b) r off c off vref a(or b) i out out1 a(or b) + + - - 1 m s 5ma blanker sense comparator comparator output monostable reset 2.5v 5v from the low-side gate drivers load a (or b ) blanking time monostable vs a (or b) to gate logic (0) (1)
15/53 AN1762 application note figure 15. pwm output current regulation waveforms (l6207 only). figure 16 shows the magnitude of the off time t off versus c off and r off values. it can be approximately calculated from the equations: t rcfall = 0.6 r off c off t off = t rcfall + t dt = 0.6 r off c off + t dt where r off and c off are the external component values and t dt is the internally generated dead time with: 20k w r off 100k w 0.47nf c off 100nf t dt = 1s (typical value) therefore: t off(min) = 6.6s t off(max) = 6ms these values allow a sufficient range of t off to implement the drive circuit for most motors. the capacitor value chosen for c off also affects the rise time t rcrise of the voltage at the pin rc a (or rc b ). the rise time t rcrise will only be an issue if the capacitor is not completely charged before the next time the monostable is triggered. therefore, the on time t on , which depends by motors and supply parameters, has to off bc dd a t on t off bc on 2.5v 0 slow decay slow decay 1 m s t blank t rcrise t rcrise synchronous rectification 1 m s t blank 5v v rc v sense v ref i out v ref r sense d02in1351 t off 1 m s t dt 1 m s t dt t rcfall t rcfall
AN1762 application note 16/53 be bigger than t rcrise for allowing a good current regulation by the pwm stage. furthermore, the on time t on can not be smaller than the minimum on time t on(min) . t rcrise = 600 c off 3.11.1 off-time selection and minimum on-time (l6207 only) figure 16 also shows the lower limit for the on time t on for having a good pwm current regulation capacity. it has to be said that t on is always bigger than t on(min) because the device imposes this condition, but it can be smaller than t rcrise - t dt . in this last case the device continues to work but the off time t off is not more con- stant. so, small c off value gives more flexibility for the applications (allows smaller on time and, therefore, higher switching frequency), but, the smaller is the value for c off , the more influential will be the noises on the circuit performance. figure 16. off-time selection and minimum on-time (l6207 only). t on t on min () >1.5 m s (typ. value) = t on t rcrise t dt C > ? ? ? 0.1 1 10 100 1 10 100 1 . 10 3 1 . 10 4 coff [ nf] to f f [u s] 0.1 1 10 100 1 10 100 coff [nf] to n ( m in ) [ u s] r = 20 k w r = 47 k w r = 100 k w
17/53 AN1762 application note 3.11.2 slow decay mode (l6207 only) figure 17 shows the operation of the bridge in the slow decay mode. at the start of the off time, the lower power mos is switched off and the current recirculates around the upper half of the bridge. since the voltage across the coil is low, the current decays slowly. after the dead time the upper power mos is operated in the synchro- nous rectification mode. when the monostable times out, the lower power mos is turned on again after some delay set by the dead time to prevent cross conduction. figure 17. slow decay mode output stage configurations in some conditions (short off-time, very low regulated current, high motor winding l / r) the system may need an on-time shorter than 1.5s. in these cases the pwm current controller can loose the regulation. figure 18 shows the operation of the circuit in this condition. when the current first reaches the threshold, the bridge is turned off for a fixed time and the current decays. during the following on-time current increases above the threshold, but the bridge cannot be turned off until the minimum 1.5s on-time expires. since current in- creases more in each on-time than it decays during the off-time, it keeps growing during each cycle, with steady state asymptotic value set by duty-cycle and load dc resistance: the resulting peak current will be i pk = v s d / r load , where d = t on / (t on + t off ) is the duty-cycle and r load is the load dc resistance. figure 18. minimum on-time can cause the pwm controller to loose the regulation (l6207 only). a) on time b) 1 m s dead time c) synchronous rectification d) 1 m s dead time d01in1336 needed t on is less than 1.5 s minimum t on is about 1.5 s v ref / r sense
AN1762 application note 18/53 3.12 over current protection to implement an over current (i.e. short circuit) protection, a dedicated over current detection (ocd) circuitry (see figure 19 for a simplified schematic) senses the current in each high side. power dmos are actually made up with thousands of individual identical cells, each carrying a fraction of the total current flowing. the current sensing element, connected in parallel to the power dmos, is made only with few such cells, having a 1:n ratio compared to the power dmos. the total drain current is split between the output and the sense element ac- cording to the cell ratio. sensed current is, then, a small fraction of the output current and will not contribute significantly to power dissipation. figure 19. over current detection simplified circuitry. + over temperature i ref i ref (i 1a +i 2a ) / n i 1a / n power sense 1 cell power sense 1 cell power dmos n cells power dmos n cells high side dmoss of the bridge a out1 a out2 a vs a i 1a i 2a i 2a / n ocd comparator to gate logic internal open-drain r ds(on) 40 w typ. c ena r ena r cla . en a ocd a progcl a, +5v 1.2v - + m c or logic + over temperature i ref (i 1a +i 2a ) / n i 1a / n power sense 1 cell power sense 1 cell power dmos n cells power dmos n cells high side dmoss of the bridge a out1 a out2 a vs a i 1a i 2a i 2a / n ocd comparator to gate logic internal open-drain r ds(on) 40 w typ. c en r en en a +5v m c or logic l6206 l6205, l6207
19/53 AN1762 application note this sensed current is compared to an internally generated reference (adjustable through the external resistors r cla and r clb for l6206) to detect an over current condition. an internal open drain mosfet turns on when the sum of the currents in the bridges 1a and 2a or 1b and 2b reaches the threshold (5.6a typical value for l6205 and l6207; adjustable through the external resistors r cla and r clb for l6206); in l6205 and l6207 the open drain are internally connected to the en pins; with l6206 ocd pins should be connected to en pins to allow the protection working. to ensure an over current protection, connect these pins to an external rc network (see figure 19). figure 20 shows the device operating in overcurrent condition (short to ground). when an over current is de- tected the internal open drain mosfet pull the en pin to gnd switching off all 4 power dmos of the interested bridge and allowing the current to decay. under a persistent over current condition, like a short to ground or a short between two output pins, the external rc network on the en pin (see figure 19) reduces the r.m.s. value of the output current by imposing a fixed disable-time after each over current occurrence. the values of r en and c en are selected to ensure proper operation of the device under a short circuit condition. when the current flowing through the high side dmos reaches the ocd threshold (5.6 a typ. for l6205 and l6207, adjustable for l6206), after an internal propagation delay (t ocd(on) ) the open drain starts discharging c en . when the en pin voltage falls below the turn-off threshold (v th(off) ) all the power dmos turn off after the internal propagation delay (t d(off)en ). the current begins to decay as it circulates through the freewheeling diodes. since the dmos are off , there is no current flowing through them and no current to sense so the ocd circuit, after a short delay (t ocd(off) ), switches the internal open drain device off, and r en can charge c en . when the voltage at en pin reaches the turn-on threshold (v th(on) ), after the t d(on)en delay, the dmos turn on and the current restarts. even if the maximum output current can be very high, the external rc network provides a disable time (t disable ) to ensure a safe r.m.s. value (see figure 20). figure 20. over current operation. the maximum value reached by the current depends on its slew-rate, so on the short circuit nature and supply voltage, and on the total intervention delay (t delay ). it can be noticed that after the first current peak, the max- imum value reached by the output current becomes lower, because the capacitor on en pins is discharged start- ing from a lower voltage, resulting in a shorter t delay . the following approximate relations estimate the disable time and the first ocd intervention delay after the short circuit (worst case). en output current v th(off) t d( off) en i s over t ocd( on) t disable t ocd(off) t delay t en(fall) t en(rise) v en(low) en output current t disable v th(on) t d( on)en
AN1762 application note 20/53 the time the device remains disabled is: where v en(low) is the minimum voltage reached by the en pin, and can be estimated with the relation: the total intervention time is where t ocd(off) , t ocd(on) , t d(on)en , t d(off)en , and r opdr are device intrinsic parameters, v dd is the pull-up voltage applied to r en . the external rc network, c en in particular, must be chosen obtaining a reasonable fast ocd intervention (short t delay ) and a safe disable time (long t disable ). figure 21 shows both t disable and t delay as a function of c en : at least 100s for t disable are recommended, keeping the delay time below 12s at the same time. the internal open drain can also be turned on if the device experiences an over temperature (ovt) condition. the ovt will cause the device to shut down when the die temperature exceeds the ovt threshold (t j >165 c typ.). since the ovt is also connected directly to the gate drive circuits (see figure 1 to figure 3), all the power dmos will shut down, even if en pin voltage is still over v th(off) . when the junction temperature falls below the ovt turn-off threshold (150 c typ.), the open drain turn off, c en is recharged up to v th(on) and then the powerdmos are turned on back. en on d rise en off ocd disable t t t t ) ( ) ( ) ( + + = ) ( ) ( ) ( ln on th dd low en dd en en rise en v v v v c r t - - = en opdr off ocd en off d c r t t off th low en e v v + - = ) ( ) ( ) ( ) ( en off d fall en on ocd delay t t t t ) ( ) ( ) ( + + = ) ( ) ( ln off th dd en opdr fall en v v c r t =
21/53 AN1762 application note figure 21. typical disable and delay time as a function of c en , for several values of r en . 3.13 adjusting the over current detection trip point (l6206 only) the l6206 allows the user to set the over current detection threshold separately for the two full bridges con- necting two resistors (r cl ) to pins progcl a and progcl b . the ocd threshold (i sover ) follows the equa- tions: Ci sover = 5.6a 30% at -25 c < t j < 125 c if r cl = 0 w ( progcl connected to gnd) Ci sover = 10% at -25 c < t j < 125 c if 5k w < r cl < 40k w figure 22 shows the ocd threshold versus r cl value in the range from 5k w to 40k w . 110100 0.1 1 10 t delay [s] c en [nf] 110100 1 10 100 1 . 10 3 c en [nf] t disable [s] r en = 220 k w r en = 100 k w r en = 47 k w r en = 33 k w r en = 10 k w 22100 r cl ----------------
AN1762 application note 22/53 figure 22. output current detection threshold versus r cl value (l6206 only) the over current detection threshold can also be adjusted through an external reference voltage, as shown in figure 23. the external reference voltage source should be able to sink current (about 300 a maximum). more- over, if supply voltage is provided to the l6206 before v ext , and its en pins are at a high logic level, the device starts working with minimum ocd threshold (actually the capacitor placed at the bottom of r cl allows a short start-up time with higher ocd threshold). v ext can also be obtained through a pwm output of a c, adding a series resistor to obtain a low-pass filter. the ocd threshold (i sover ) follows the equation: i sover = 10%, at -25 c < t j < 125 c if 0.5 a < i sover < 4.5 a figure 23. adjusting the ocd threshold through an external reference voltage (l6206 only) 5k 10k 15k 20k 25k 30k 35k 40k 0 0.5 1 1.5 2 2.5 3 3.5 5 r cl [ w ] 4 4.5 i sover [a] 18416.7 1.2v vext C () r cl ---------------------------------------------------------- - r cl progcl a l6206 v ext = 0 1.2 v
23/53 AN1762 application note 3.14 paralleling two full bridges 3.14.1paralleling two full bridges to get a single full bridge the outputs of l6205, l6206, l6207 can be paralleled to increase the output current capability or reduce the power dissipation in the device at a given current level. it must be noted, however, that the internal wire bond connections from the die to the power or sense pins of the package must carry current in both of the associated half bridges (see figure 24). when the two halves of one full bridge (for example out1 a and out2 a ) are con- nected in parallel, the peak current rating is not increased since the total current must still flow through one bond wire on the power supply or sense pin. in addition, the over current detection senses the sum of the current in the upper devices of each bridge (a or b) so connecting the two halves of one bridge in parallel does not in- crease the over current detection threshold. figure 24. v s and sense pins maximum current handling this configuration has to be used when two separate loads are driven, since the ics has only two enable in- puts, one for the full bridge a and the other for the bridge b. in this case pulling to gnd one of the two enable pins will disable only one load (see figure 25). this configuration can also be used if a 5.6a ocd threshold is desired (instead of 11.2a). half bridge 1 and the half bridge 2 of the bridge a are connected in parallel and the same done for the bridge b as shown in figure 25. in this configuration, the peak current for each half bridge is still limited by the bond wires for the supply and sense pins so the dissipation in the device will be reduced, but the peak current rating is not increased. using this configuration with l6206, two separate resistors connected to pins progcl a and progcl b must be used. with l6207, two separate rc network should be used on rc pins. when two different loads are driven (see figure 25) by the two equivalent half bridges, two separate sensing resistors are needed, while if the two equivalent half bridges drive two separate loads, they must be connected from the out pins to v s (see figure 25) to make the pwm current control working properly. in this configuration, the resulting bridge has the following characteristics (typical values). - equivalent device: full bridge - r ds(on) 0.15 w typ. value @ t j = 25c - 2.8a max rms load current - 5.6a ocd threshold over current detection vs a out2 a sense a bridge a 2.8a rms 5.6a peak sourced: i out1 + i out2 = i supply < 2.8a rms, 5.6a pk. sourced current ocd threshold: i out1 + i out2 = 5.6a typ. out1 a sinked: i out1 + i out2 = i sense < 2.8a rms, 5.6a pk. over current detection vs b out2 b sense b bridge b 2.8a rms 5.6a peak sourced: i out1 + i out2 = i supply < 2.8a rms, 5.6a pk. sourced current ocd threshold: i out1 + i out2 = 5.6a typ. out1 b vs a out2 a sense a bridge a 2.8a rms 5.6a peak out1 a sinked: i out1 + i out2 = i sense < 2.8a rms, 5.6a pk. vs b out2 b sense b bridge b 2.8a rms 5.6a peak out1 b
AN1762 application note 24/53 figure 25. parallel connection with lower overcurrent threshold (l6205, l6206, l6207) c p c boot r p d 2 d 1 c 2 out1 a ocd a ocd b 1 5 21 18 19 8 16 out2 a gnd gnd gnd gnd progcl a out2 b out1 b vs a power ground signal ground + - vs 8-52v dc 4 vs b vcp vboot c 1 sense a 20 in a in1 a in2 a 2 6 7 9 en a en b c en r en en 23 in2 b 12 in1 b in b 11 14 24 17 3 15 22 sense b r cla 10 progcl b 13 r clb c p c boot r p d 2 d 1 c 2 out1 a 4 18 16 15 7 13 out2 a gnd gnd gnd gnd out2 b out1 b vs a power ground signal ground + - vs 8-52v dc vs b vcp vboot c 1 sense a 17 6 5 14 3 12 19 sense b 8 10 in a in2 b in2 a 2 in1 a 1 in1 b in b 9 en b en a c en r en en 11 20 l6205 l6206 c p c boot r p d 2 d 1 c 2 out1 a 5 21 16 15 8 16 out2 a gnd gnd gnd gnd out2 b out1 b vs a power ground signal ground + - vs 8-52v dc vs b vcp vboot c 1 sense a 20 6 5 17 3 15 22 sense b 10 12 in a in2 b in2 a 2 in1 a 1 in1 b in b 11 en b en a c en r en en 14 23 l6207 13 vref b 24 vref a 9 rc b r b c b 4 rc a r a c a v ref = 0 1 v r sense load load load load load r sense load vs vs
25/53 AN1762 application note for some applications the recommended configuration is half bridge 1 of bridge a paralleled with the half bridge 1 of the bridge b, and the same for the half bridges 2 as shown in figure 26. figure 26. parallel connection for higher current (l6205 and l6206 only) this configuration cannot be used with l6207, because of its internal pwm current controllers that work sepa- rately for bridge a and bridge b. using this configuration with the l6207 may damage the device. in this configuration the resulting bridge has the following characteristics (typical values). - equivalent device: full bridge - r ds(on) 0.15 w typ. value @ t j = 25c - 5.6a max rms load current - 11.2a ocd threshold it should be noted that using two separate loads for the two equivalent half bridges the maximum current cannot be sourced or sinked simultaneously by the two equivalent half bridges (for example to drive two separate loads), due to the 5.6 a maximum current limit for v s and sense pins (see figure 24). when a single load is driven (see figure 26) r cla and r clb resistors connected to progcl pins of l6206 should have the same value. c p c boot r p d 2 d 1 c 2 out1 a load ocd a ocd b 1 5 21 18 19 8 16 out2 a gnd gnd gnd gnd progcl a out2 b out1 b vs a power ground signal ground + - vs 8-52v dc 4 vs b vcp vboot c 1 sense a 20 in2 in1 a in2 b 12 6 7 9 en a en b r en en 23 in1 b 11 in2 a in1 2 14 24 17 3 15 22 sense b r cla 10 c en progcl b 13 r clb out1 a 4 7 16 15 18 13 out1 b gnd gnd gnd gnd out2 b out2 a vs a power ground signal ground + - vs 8-52v dc vs b vcp vboot c 1 sense a 17 6 5 en b 11 14 3 12 19 sense b load 8 en a c en r en en 20 1 in2 in1 a in2 b 10 in1 b 9 in2 a in1 2 c p c boot r p d 2 d 1 c 2 l6205 l6206
AN1762 application note 26/53 3.14.2paralleling the four half bridges to get a single half bridge it is also possible to parallel the four half bridges to obtain a simple half bridge as shown in figure 27. this configuration cannot be used with l6207, because of its internal pwm current controllers that work sepa- rately for bridge a and bridge b. using this configuration with the l6207 may damage the device. the resulting half bridge has the following characteristics (typical values). - equivalent device: half bridge - r ds(on) 0.075 w typ. value @ t j = 25c - 5.6a max rms load current - 11.2a ocd threshold with l6206 r cla and r clb resistors connected to progcl pins must have the same value. figure 27. paralleling the four half bridges (l6205 and l6206 only) c p c boot r p d 2 d 1 c 2 out1 a 4 7 16 15 18 13 out1 b gnd gnd gnd gnd out2 b out2 a vs a power ground signal ground + - vs 8-52v dc vs b vcp vboot c 1 sense a 17 6 5 en b 11 14 3 12 19 sense b 8 en a c en r en en 20 1 in1 a in2 b 10 in1 b 9 in2 a 2 load in c p c boot r p d 2 d 1 c 2 out1 a load ocd a ocd b 1 5 21 18 19 8 16 out2 a gnd gnd gnd gnd progcl a out2 b out1 b vs a power ground signal ground + - vs 8-52v dc 4 vs b vcp vboot c 1 sense a 20 in in1 a in2 a 2 6 7 9 en a en b c en r en en 23 in2 b 12 in1 b 11 14 24 17 3 15 22 sense b r cla 10 progcl b 13 r clb l6205 l6206
27/53 AN1762 application note 3.15 power management even when operating at current levels well below the maximum ratings of the device, the operating junction tem- perature must be kept below 125 c. figure 28 shows the ic dissipated power versus the r.m.s. load current, in the case of a single ic driving two loads (for instance 2 dc motors or a two-phase stepper motor) or a single ic, with two full bridges paralleled (see paralleling two full bridges section ) driving one load (for instance 1 dc motor or one phase of a two- phase stepper motor) and assuming the supply voltage is 24v. figure 28. ic dissipated power versus output current. 3.15.1 maximum output current vs. selectable devices figure 29 reports a performance comparison between different devices of the powerspin family, for different packages and in paralleled configuration, with the following assumptions: - each equivalent full bridge drives a load. - supply voltage: 24 v; switching frequency: 30 khz. - t amb = 25 c, t j = 125 c. - maximum r ds(on) (taking into account process spread) has been considered, @ 125 c. - maximum quiescent current i q (taking into account process spread) has been considered. - pcb is a fr4 with a dissipating copper surface on the top side of 6 cm 2 (with a thickness of 35 m) for so and powerdip packages (d, n suffixes). - pcb is a fr4 with a dissipating copper surface on the top side of 6 cm 2 (with a thickness of 35 m), 16 via holes and a ground layer for the powerso package (pd suffix). - for each device configuration (on the x axis) y axis reports the maximum output (load) current. - 2 x device means that the two loads are driven by two equivalent full bridges obtained paralleling two full bridg- es for each of the two ic used. the current reported in figure 29 is the maximum output current an equivalent full bridge (a paralleled ic). 0 0.5 1 1.5 2 2.5 3 0 2 4 6 8 10 i out [a] p d [w] f sw = 30 khz (synch. slow decay) no pwm 2 full bridges paralleled 2 full bridges driving one load driving two loads
AN1762 application note 28/53 figure 29. maximum output current vs. selectable devices. 3.15.2 power dissipation formulae for different sequences figure 30 to figure 33 are screenshots of a spreadsheet that helps calculating power dissipation in specified conditions (application and motor data), and estimates the resulting junction temperature for a given package and copper area available on the pcb [4]. the model assumes that the device is driving a two-phase bipolar stepper motor and that a pwm current control with slow decay recirculation technique is implemented (l6207 integrates the pwm controller); it considers pow- er dissipation during the on-time and the off-time, rise and fall time (when a phase change occurs) considering the operating sequence (normal, wave or half step mode), the switching losses and the quiescent current pow- er dissipation. l 6 2 2 x d l 6 2 2 x n l 6 2 2 x p d l 6 2 0 x d l 6 2 0 x n l 6 2 0 x p d 2 x l 6 2 2 x d 2 x l 6 2 2 x n 2 x l 6 2 2 x p d 2 x l 6 2 0 x d 2 x l 6 2 0 x n 2 x l 6 2 0 x p d 0.50 1.00 1.50 2.00 2.50 3.00 load current [a]
29/53 AN1762 application note figure 30. definition of parameters for the three different sequences. the current in only one phase is shown. figure 31. input data. t r t f t load d d d d i i pk i t t i load normal t r t f t load d d d d i i pk i t t/2 i load wave t r t f t load d d d d i i pk i t t i load half step input data maximum drain-source on resistance ron = 5.60e-01 [ohm] average value between high-side and low-side maximum diode voltage vd = 1.20e+00 [v] quiescent current iq = 5.50e-03 [ma] maximum bemf voltage vb = 1.50e+01 [v] motor inductance lm = 7.90e-03 [h] motor resistance rm = 6.60e+00 [ohm] supply voltage vs = 2.40e+01 [v] peak current ipk = 1.00e+00 [a] off-time toff = 1.50e-05 [s] step frequency fck = 1.00e+03 [hz] sensing resistance rs = 5.00e-01 [ohm] decay type - "slow" = synchronous slow decay "fast" = quasi-synchronous fast decay stepping sequence - "normal", "half" or "wave" slow wave device input values motor input value s application input values
AN1762 application note 30/53 figure 32. power dissipation formulae and results. result powerdmos commutation time tcom = 9.60e-08 [s] vs / (250v/ m s) rise time trise = 4.03e-04 [s] fall time tfall = 3.16e-04 [s] normal mode half or wave mode duty cycle d = 6.25e-01 - vb / vs sync. slow decay switching frequency fsw = 2.50e+04 [hz] (1-d) / toff current ripple d i = 2.85e-02 [a] (vs - vb)*d / (lm* fsw) period t = 2.00e-03 [s] 2 / fck 4 / fck 2 / fck normal mode half mode wave mode load time tload = 5.97e-04 [s] t- tr i s e - t f a l l (3/4)t-rise (t/2)-trise normal mode half mode wave mode average cur- rent during load time i = 9.86e-01 [a] r.m.s. current during load time irms = 9.86e-01 [a] rise time dissipating energy erise = 1.50e-04 [j] fall time dissipating energy efall = 3.62e-04 [j] mormal mode half or wave mode load time diss. energy eload = 6.50e-05 [j] 2ron irms 2 tload sync. slow decay ipk rm 2 ipk ron ipk rs vs + C C C () vs --------------------------------------------------------------------------------------------------------------- lm rm rs 2ron ++ --------------------------------------------- - ln C vs ipk rm 2 + ipk ron ipk rs vs + + () ------------------------------------------------------------------------------------------------------------ - lm rm 2 ron rs + + () ------------------------------------------------------ - ln C vs 2 vd C () ipk rm ipk rs vs 2 vd C + + () ------------------------------------------------------------------------------------------ - lm rm rs + () ---------------------------- ln C ipk i d 2 ---- - C ipk ipk i d C () i 2 d 3 ------- + 2ron ipk 2 trise 3 -------------- - 2ron ipk 2 tfall 3 ------------ - 2vdtfall vs C 2vd + () rm rs + () -------------------------------------- m ipk rm ipk rs vs 2 vd C + + () 1 t C fall lm --------------- - rm rs + () exp C rm rs + () 2 -------------------------------------------------------------------------------- - +
31/53 AN1762 application note figure 33. thermal data inputs and results. commutatiion time dissipating pw ecom = 6.78e-05 [j] 2vs i tcom tload fsw quiescent dissipating pw pq = 1.32e-01 [w] vs iq total dissi- pating power p = 1.36e+00 [w] (erise + efall + eload + ecom) + pq 2 t --- input data packa g e so2 4 copper area 4.0 110 sq. cm copper area is on same side of the device ground layer n/a ambient temperature 50 -25 100 oc results thermal resistance junction to ambient 53.36 oc / w thermal resistance junction to pins / slug 14.00 oc / w estimated junction temperature 122.66 oc estimated pins / slu g temperature 103.60
AN1762 application note 32/53 4 application example (l6207) application data motor data rotation speed: 300 rpm (f ck = 1khz) winding resistance: 6.6 w winding peak current: 1a winding inductance: 7.9mh maximum ripple: 50ma step angle: 1.8/step supply voltage: 24v 5% maximum bemf at 300rpm: 15v sequence: wave mode 4.1 decay mode, sensing resistors and reference voltage. referring to approximated formulae in figure 32, it's possible to calculate the duty-cycle (d), the switching fre- quency (f sw ), the current ripple ( d i). with a 15 s off-time, we will have: d @ 63%, f sw @ 25khz, d i @ 29ma. the on-time is t on = d / f sw @ 25s, which is far from the minimum allowed (1.5s), so slow decay can be used. the bulk capacitor need to withstand at least 24v + 5% + 25% @ 32v. a 50v capacitor will be used. allowing a voltage ripple of 200mv, the capacitor esr should be lower than 200mv / 1a = 200m w ; the ac current capa- bility should be about 1a. providing a reference voltage of 0.5v, 0.5 w sensing resistor are needed. the resistors power rating is about p r @ i rms 2 r sense d @ 0.32w. two 1 w - 0.25w - 1% resistors in parallel are used. the charge pump uses rec- ommended components (1n4148 diodes, ceramic capacitors and a 100 w resistor to reduce emi). r = 18k w , c = 1.2 nf are connected to the rc pins, obtaining t off @ 16s. on the en pins 5.6nf capacitors have been placed, and the pins are driven by the c through 100k w resistors. with these values, in case of short circuit between two out pins or an out pin and gnd, the powerdmos turns off after about 1s, and t disable @ 240s. figure 34. application example. with wave drive selected, referring to figure 31 to figure 33, the dissipating power is about 1.36 w. if the am- bient temperature is lower than 50c, with 4cm 2 of copper area on the pcb and a so24 package, the estimated junction temperature is about 123c. using more copper area or a powerdip package will reduce the junction temperature. + - v s = 24 v v ref = 0.5 v en b in2 b in2 a in 1 b in 1 a v refa v refb rc a rc b gnd gnd gnd gnd sense a sense b v sa v sb v boo t cp out 1b out 2b out 1a out 2a 1n4148 1n4148 100 k w 1.2 nf ceramic 18 k w 5% 100 w 0.25w 5.6 nf ceramic 47nf ceramic 18 k w 5% 1.2 nf ceramic 100nf 50v ceramic 220nf 50v ceramic 10nf 50v ceramic 100f 50v esr<200m w l6207 c or custom logic 2-phase stepper motor + - 4 x 1 w , 0.25 w, 1% 2 k w 0.25 w 1% 18 k w 0.25 w 1% logic supply 5 v en a 100 k w 5.6 nf cera mic
33/53 AN1762 application note 5 appendix - evaluation boards 5.1 practispin practispin is an evaluation and demonstration system that can be used with the powerspin family (l62xx) of devices. a graphical user interface (gui) (see figure 35) program runs on an ibm-pc under windows and com- municates with a common st7 based interface board (see figure 36) through the rs232 serial port. the st7 interface board connects to a device specific evaluation board (target board) via a standard 34 pin ribbon cable interface. depending on the target device the practispin can drive a stepper motor, 1 or 2 dc motors or a brushless dc (bldc) motor, operating significant parameters such as speed, current, voltage, direction, accel- eration and deceleration rates from a user friendly graphic interface, and programming a sequence of movements. the software also allows evaluating the power dissipated by the selected device and, for a given package and dissipating copper area on the pcb, estimates the device's junction temperature. figure 35. practispin pc software
AN1762 application note 34/53 figure 36. practispin st7 evaluation board 5.2 eval6205n an evaluation board has been produced to help the evaluation of the device in powerdip package. it imple- ments a typical application with several added components. figure 38 shows the electrical schematic of the board; in the table below the part list is reported. cn1, cn2, cn3, cn4 2-poles connector r1 100 w resistor cn5 34-poles connector r2 700 w 0.6w resistor c1 220nf/100v ceramic or polyester capacitor r3, r4, r13 10k w resistor c2 220nf/100v ceramic or polyester capacitor r5, r6 4.7k w resistor c3 100f/63v capacitor r7, r8, r9, r10, r11, r12 1 w 0.4w resistor c4 10nf/100v ceramic capacitor r18, r14 1k w resistor c5 10f/16v capacitor r15, r19 20k w resistor c6, c7, c11 100nf capacitor r16, r20 2.2k w resistor c8, c10 470pf capacitor r21, r17 5k w trimmer c9, c12 68nf capacitor r22 12k w resistor c13 2.2nf capacitor r23 50k w trimmer d1, d2 1n4148 diode u1 l6205n d3 bzx79c5v1 5.1v zener diode u2 l6506 jp1 3-pin jumper jp2, jp3, jp4, jp5 2-pin jumper the evaluation board provides external connectors for the supply voltage, an external 5v reference for the logic inputs, four outputs for the motor and a 34-pin connector to control the main functions of the board through an external c board or the practispin tool. the board also accommodates the l6506 pwm current controller. r23 sets the pwm operating frequency. if the l6506 does not need to be used, simply connect the two v ref inputs to a voltage high enough to keep current control inactive. the practispin tool is composed of a graphic interface software running on a pc that connects with the hard- ware based on the st7 c, which contains an upgradeable firmware. this tool allows a fast and easy evaluation of the powerspin family devices, giving the ability of driving dc, bldc and stepper motors, depending on the target device. the practispin connected to the eval6205n can drive dc motors and inductive loads, allowing output voltage and current settings the pc-software also provides a power dissipation and thermal analysis section, intended to help a fast eval- uation of the device, package and dissipating copper area required by the users application, and to be a good starting point designing an application (from the power dissipation and thermal point of view).
35/53 AN1762 application note running the evaluation board in stand-alone mode, instead, r17 and r21 set the reference voltage separately for the two bridges, while r16, c9 and r20, c12 are low-pass filters to provide an external reference voltage by a pwm output of a c (see also the microstepping section). using external v ref inputs r15, r17, r19, r21 can be disconnected through jp4 and jp5, unless the practispin st7 evaluation board is used. this board, in fact, is provided with an offset cancellation circuitry trimmable through a potentiometer (see practispin docu- mentation). closing jp2 and jp3 is recommended for safe over current protection. the 5v voltage for logic inputs and for references (v refa and v refb ) is obtained from r2, d3. depending on the supply voltage, the value of resistor r2 should be changed in order to ensure a correct biasing of d3. the jumper jp1 allows choosing the 5v voltage from the internal zener diode network or pin 11 of cn5 (for ex- ample an external c board can provide 5v to the evaluation board). also cn2 connector can be used to pro- vide an external 5v voltage to the board (in that case r2, d3 should be disconnected). cn2, or pin 1 of cn5, can also be used to provide a 5v voltage to external circuits (as, for example, the practispin st7 board). in this case the current that can be drawn form the board depends on the supply voltage and on r2 value. figure 39 to figure 41 show the component placement and the two layers layout of the l6205n evaluation board. a large gnd area has been used, to guarantee minimal noise and good power dissipation for the device. figure 37. eval6205n. 5.2.1 important notes jp1 : close in int position for use with practispin st7 board c6, c7 : recommended change to 5.6 nf for safe overcurrent protection r3, r4 : recommended change to 100 k for safe overcurrent protection r5, r6 : recommended change to 100 k if en pins are driven from the cn5 connector (for example with prac- tispin st7 board) for safe overcurrent protection r17, r21 : set the maximum current obtainable through practispin (see practispin documentation) r2 : recommended change to adequate value (depending on supply voltage) to obtain 5v across d3 jp2, jp3 : close for safe overcurrent protection jp4, jp5 : close for use with practispin st7 board jp1 c6 c7 r3 r4 r6 r5 r17 r21 jp2 jp3 jp4 jp5
AN1762 application note 36/53 figure 38. eval6205n electrical schematic. pullup pullup +5v pullup 3 2 pullup 1 pullup +5v 4 pullup vccref pullup gnd int6 ext. cw ocmpa1 p4.2 int. tina0 p2.0 tinb0 p2.1 cw ocmpb1/icapb1 p4.3 tina1 p2.4 int3 toutb0 p2.3 tinb1 p2.5 touta1 p2.6 cw adc_ref int0 toutpb1 2.7 int2 r19 c9 cn3 1 2 d2 c4 c12 jp4 jp2 d3 cn1 1 2 r1 jp3 r4 d1 cn4 1 2 c6 r5 u2 l6506dip in1 5 in2 6 in3 7 in4 8 out1 14 out2 13 out3 12 out4 11 en 4 vs ens e2 15 vref 2 17 vs ens e1 10 r/c 1 vref 1 16 sy nc 3 vc c 18 os c_out 2 gnd 9 r6 jp1 1 3 2 jp5 cn2 1 2 r14 r13 c1 c2 r3 r20 cn5 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 c11 r22 r23 c13 r17 r16 r2 c5 c8 c10 r18 r21 c7 r15 r9 r10 r7 c3 r11 u1 l6205 out1b 7 out2a 18 in1 1 in2 2 sensea 3 ou t 1a 4 gnd 5 gnd 6 senseb 8 in3 9 in4 10 enb 11 vboot 12 ou t 2b 13 vsb 14 gnd 16 gnd 15 vsa 17 vcp 19 ena 20 r8 r12 in1 _2 ena limit_a _4 enb _1 in3 _3 li mit_b vref_a _2 sense_a sense_b vref_b ena in4 limi t_b in2 sense_a sense_b _1 in3 enb _4 _3 li mit_a in4 in2 in1 vrefb vrefa
37/53 AN1762 application note figure 39. eval6205n component placement. figure 40. eval6205n top layer layout. power gnd (bulk capacitor) signal gnd
AN1762 application note 38/53 figure 41. eval6205n bottom layer layout. short sense paths
39/53 AN1762 application note 5.3 eval6206n an evaluation board has been produced to help the evaluation of the device in powerdip package. it imple- ments a typical application with several added components. figure 43 shows the electrical schematic of the board; in the table below the part list is reported. cn1, cn2, cn3, cn4 2-poles connector r1 100 w resistor cn5 34-poles connector r2 700 w 0.6w resistor c1 220nf/100v ceramic or polyester capacitor r3, r4, r16 10k w resistor c2 220nf/100v ceramic or polyester capacitor r5, r6 4.7k w resistor c3 100f/63v capacitor r7, r8 50k w trimmer c4 10nf/100v ceramic capacitor r9, r10, r11, r12, r13, r14 1 w 0.4w resistor c5, c8, c10 10f/16v capacitor r15, r21 2.2k w resistor c6, c7 47nf capacitor r17, r23 20k w resistor c9, c13 68nf capacitor r18, r22 750 w resistor c11 100nf capacitor r19, r25 2.2k w resistor c12, c14 470pf capacitor r20, r26 5k w trimmer c15 2.2nf capacitor r27, r24 1k w resistor d1, d2 1n4148 diode r28 12k w resistor d3 bzx79c5v1 5.1v zener diode r29 50k w trimmer jp1 3-pin jumper u1 l6205n jp2 to jp7 2-pin jumper u2 l6506 the evaluation board provides external connectors for the supply voltage, an external 5v reference for the logic inputs, four outputs for the motor and a 34-pin connector to control the main functions of the board through an external c board or the practispin tool. the board also accomodate the l6506 pwm current controller. r29 sets the pwm operating frequency. if the l6506 does not need to be used, simply connect the two v ref inputs to a voltage high enough to keep current control inactive. the practispin tool is composed of a graphic interface software running on a pc that connects with the hard- ware based on the st7 c, which contains an upgradeable firmware. this tool allows a fast and easy evaluation of the powerspin family devices, giving the ability of driving dc, bldc and stepper motors, depending on the target device. the practispin connected to the eval6206n can drive dc motors and inductive loads, allowing output voltage and current settings the pc-software also provides a power dissipation and thermal analysis section, intended to help a fast eval- uation of the device, package and dissipating copper area required by the users application, and to be a good starting point designing an application (from the power dissipation and thermal point of view). running the evaluation board in stand-alone mode, instead, r20 and r26 set the reference voltage separately for the two bridges, while r19, c9 and r25, c13 are low-pass filters to provide an external reference voltage by a pwm output of a c (see also the microstepping section). using external v ref inputs r17, r20, r23, r26 can be disconnected through jp6 and jp7, unless the practispin st7 evaluation board is used. this board, in fact, is provided with an offset cancellation circuitry trimmable through a potentiometer (see practispin docu- mentation). closing jp4 and jp5, r7 and r8 allow adjusting the over current detection threshold separately for the two full bridges. leaving jp4 and jp5 opened, the ocd threshold can be programmed providing reference voltages at the bottom of r7 and r8, through pins 27 and 29 of cn5. r15, r18, c8, r21, r22, c10 provide low-pass filtering to obtain these reference voltages from an external pwm output of a c. closing jp2 and jp3 allows over current protection to work, connecting each en pin to the corresponding ocd pin. the 5v voltage for logic inputs and for references (v refa and v refb ) is obtained from r2, d3. depending on the supply voltage, the value of resistor r2 should be changed in order to ensure a correct biasing of d3. the jumper jp1 allows choosing the 5v voltage from the internal zener diode network or pin 11 of cn5 (for ex- ample an external c board can provide 5v to the evaluation board). also cn2 connector can be used to pro- vide an external 5v voltage to the board (in that case r2, d3 should be disconnected). cn2, or pin 1 of cn5,
AN1762 application note 40/53 can also be used to provide a 5v voltage to external circuits (as, for example, the practispin st7 board). in this case the current that can be drawn form the board depends on the supply voltage and on r2 value. figure 44 to figure 46 show the component placement and the two layers layout of the l6206n evaluation board. a large gnd area has been used, to guarantee minimal noise and good power dissipation for the device. figure 42. eval6206n. 5.3.1 important notes jp1 : close in int position for use with practispin st7 board c6, c7 : recommended change to 5.6 nf for safe overcurrent protection r3, r4 : recommended change to 100 k for safe overcurrent protection r5, r6 : recommended change to 100 k if en pins are driven from the cn5 connector (for example with prac- tispin st7 board), for safe overcurrent protection r20, r26 : set the maximum current obtainable through practispin (see practispin documentation) r2 : recommended change to adequate value (depending on supply voltage) to obtain 5v across d3 jp2, jp3 : close to allow overcurrent protection jp4, jp5 : close for on-board ocd threshold adjusting through r7, r8 jp6, jp7 : close for use with practispin st7 board jp1 c7 c6 r4 r3 r6 r5 r20 r26 r2 jp3 jp5 jp2 jp4 jp6 jp7
41/53 AN1762 application note figure 43. eval6206n electrical schematic. pullup 3 pullup vccref pu llu p 2 pullup gnd 4 +5v 1 +5v pullup pullup pullup cw toutb0 p2.3 touta1 p2.6 int2 adc_ref int6 ext. cw tina1 p2.4 cw int. int0 tina0 p2.0 toutpb1 2.7 tinb1 p2.5 ocmpa1 p4.2 cw ocmpb1/icapb1 p4.3 cw tinb0 p2.1 int3 jp6 c2 r19 r5 jp1 1 3 2 r20 r15 cn1 1 2 r4 r26 jp2 r17 c15 r18 cn2 1 2 r22 u2 l6506dip in1 5 in2 6 in3 7 in4 8 out1 14 out2 13 out3 12 out4 11 en 4 vsense2 15 vref 2 17 vsense1 10 r/c 1 vref 1 16 sy nc 3 vcc 18 osc_out 2 gnd 9 d1 cn5 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 c6 c4 c1 c7 r24 r27 r8 r1 r16 r21 r23 d2 r9 cn4 1 2 c10 r2 c11 c9 r28 c13 r7 r29 c12 c8 r25 c14 jp7 cn3 1 2 d3 c5 r6 r3 jp3 jp5 u1 l6206 in1 1 in2 2 sensea 3 progcla 24 out1a 5 gnd 6 gnd 7 out1b 8 progclb 13 senseb 10 in3 11 in4 12 ocdb 9 enb 14 vboot 15 out2b 16 vsb 17 gnd 18 gnd 19 vsa 20 out2a 21 vcp 22 ena 23 ocda 4 r12 r14 r10 c3 jp4 r13 r11 _4 sense_b in4 _4 in2 _1 ena sense_a sense_b _3 in4 sense_a vref_a oc db en b _3 progcla ena progclb in1 in3 vrefa progcla ocda _1 enb vrefb in3 in2 _2 _2 in1 progclb oc da vref_b ocdb
AN1762 application note 42/53 figure 44. eval6206n component placement. figure 45. eval6206n top layer layout. power gnd (bulk capacitor) signal gnd
43/53 AN1762 application note figure 46. eval6206n bottom layer layout. short sense paths
AN1762 application note 44/53 5.4 eval6206pd an evaluation board has been produced to help the evaluation of the device in powerso package. it implements a typical application with several added components. figure 48 shows the electrical schematic of the board; in the table below the part list is reported. cn1, cn2, cn3, cn4 2-poles connector jp2 to jp5 2-pin jumper cn5 34-poles connector r1 750 w 0.6w resistor c1 220nf/100v ceramic or polyester capacitor r2, r3, r26 10k w resistor c2 220nf/100v ceramic or polyester capacitor r4, r5 4.7k w resistor c3 100f/63v capacitor r6, r7 50k w trimmer c4 10nf/100v ceramic capacitor r8, r9, r10, r11 0.4 w 1w resistor c5, c8, c10 10f/16v capacitor r12, r19 20k w resistor c6, c7 100nf capacitor r13, r14, r17, r20 2.2k w resistor c9, c13 68nf capacitor r15, r18 750 w resistor c11 100nf capacitor r16, r22 5k w trimmer c12, c15 470pf capacitor r23, r21 1k w resistor c14 2.2nf capacitor r24 12k w resistor d1 bat46sw diodes r25 50k w trimmer d2 bzx79c5v1 5.1v zener diode u1 l6205n jp1 3-pin jumper u2 l6506 the evaluation board provides external connectors for the supply voltage, an external 5v reference for the logic inputs, four outputs for the motor and a 34-pin connector to control the main functions of the board through an external c board or the practispin tool. the board also accomodate the l6506 pwm current controller. r25 sets the pwm operating frequency. if the l6506 does not need to be used, simply connect the two v ref inputs to a voltage high enough to keep current control inactive. the practispin tool is composed of a graphic interface software running on a pc that connects with the hard- ware based on the st7 c, which contains an upgradeable firmware. this tool allows a fast and easy evaluation of the powerspin family devices, giving the ability of driving dc, bldc and stepper motors, depending on the target device. the practispin connected to the eval6206pd can drive dc motors and inductive loads, allow- ing output voltage and current settings the pc-software also provides a power dissipation and thermal analysis section, intended to help a fast eval- uation of the device, package and dissipating copper area required by the users application, and to be a good starting point designing an application (from the power dissipation and thermal point of view). running the evaluation board in stand-alone mode, instead, r16 and r22 set the reference voltage separately for the two bridges, while r14, c9 and r20, c13 are low-pass filters to provide an external reference voltage by a pwm output of a c (see also the microstepping section). using external v ref inputs r12, r16, r19, r22 should be disconnected, unless the practispin st7 evaluation board is used. this board, in fact, is provided with an offset cancellation circuitry trimmable through a potentiometer (see practispin documentation). closing jp4 and jp5, r6 and r7 allow adjusting the over current detection threshold separately for the two full bridges. leaving jp4 and jp5 opened, the ocd threshold can be programmed providing reference voltages at the bottom of r6 and r7, through pins 27 and 29 of cn5. r13, r15, c8, r17, r18, c10 provide low-pass filtering to obtain these reference voltages from an external pwm output of a c. closing jp2 and jp3 allows over current protection to work, connecting each en pin to the corresponding ocd pin. the 5v voltage for logic inputs and for references (v refa and v refb ) is obtained from r1, d2. depending on the supply voltage, the value of resistor r1 should be changed in order to ensure a correct biasing of d2. the jumper jp1 allows choosing the 5v voltage from the internal zener diode network or pin 11 of cn5 (for ex- ample an external c board can provide 5v to the evaluation board). also cn2 connector can be used to pro- vide an external 5v voltage to the board (in that case r1, d2 should be disconnected). cn2, or pin 1 of cn5, can also be used to provide a 5v voltage to external circuits (as, for example, the practispin st7 board). in this
45/53 AN1762 application note case the current that can be drawn form the board depends on the supply voltage and on r1 value. figure 49 to figure 51 show the component placement and the two layers layout of the l6206pd evaluation board. a large gnd area has been used, to guarantee minimal noise and good power dissipation for the device. figure 47. eval6206pd. 5.4.1 important notes jp1 : close in int position for use with practispin st7 board c6, c7 : recommended change to 5.6 nf for safe overcurrent protection r2, r3 : recommended change to 100 k for safe overcurrent protection r4, r5 : recommended change to 100 k if en pins are driven from the cn5 connector (for example with prac- tispin st7 board) for safe overcurrent protection r16, r22 : set the maximum current obtainable through practispin (see practispin documentation) r1 : recommended change to adequate value (depending on supply voltage) to obtain 5v across d2 jp2, jp3 : close to allow overcurrent protection jp4, jp5 : close for on-board ocd threshold adjusting through r6, r7 cn5 : vrefa and vrefb positions are inverted if compared to other eval62xx boards. jp1 c7 c6 r3 r2 r5 r4 r16 r22 r1 jp4 jp5 jp2 jp3 cn5
AN1762 application note 46/53 figure 48. eval6206pd electrical schematic. pullup pullup pullup vccref pullup pullup pullup +5v pullup +5v adc_ref int3 l6206pd int2 a0in6 p7.6 tina0 p2.0 tina1 p2.4 toutpb1 2.7 a1in6 p8.1 ocmpb1/icapb1 p4.3 tinb0 p2.1 touta1 p2.6 int0 int6 tinb1 p2.5 toutb0 p2.3 cw cw cw cw cw int. ext. ocmpa1 p4.2 r15 r13 r18 r17 c8 c10 cn4 1 2 cn3 1 2 c12 c15 r23 r21 r11 r24 r25 r12 r14 r16 r20 r7 r6 c9 c13 c7 c6 jp3 jp2 cn1 1 2 cn2 1 2 c5 d2 r1 c2 c1 u2 in1 5 in2 6 in3 7 in4 8 out1 16 out2 15 out3 14 out4 13 en 4 vsense2 17 vref 2 19 vsense1 12 r/c 1 vref 1 18 sy nc 3 vc c 20 osc_out 2 gn d 9 nc 10 nc 11 c11 c14 r22 r19 r26 cn5 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 jp1 1 3 2 d1 1 3 2 c4 r5 r3 r4 r2 r10 jp4 jp5 r8 c3 u1 gnd 36 in1 10 gnd 1 sensea 12 vboot 30 in2 11 gnd 18 vsb 33 gnd 19 progcla 9 in3 26 vsa 4 vcp 7 progclb 28 enb 29 en a 8 in4 27 ocdb 24 ocda 13 out1a 15 senseb 25 out1b 22 out2a 5 out2b 32 nc 2 nc 3 nc 6 nc 14 nc 16 nc 17 nc 20 nc 21 nc 23 nc 31 nc 34 nc 35 r9 pr ogc la progclb sense_b sense_a in1 in4 in2 in3 _2 _1 _3 _4 vref_a vref_b sense_b sense_a ocdb _3 oc da _1 _2 _4 in4 progcla ena in2 ocdb enb in3 in1 ocda sen se_a pr ogc lb vrefa vrefb enb ena sen se_b
47/53 AN1762 application note figure 49. eval6206pd component placement. figure 50. eval6206pd top layer layout. power gnd (bulk capacitor) signal gnd
AN1762 application note 48/53 figure 51. eval6206pd bottom layer layout. signal gnd
49/53 AN1762 application note 5.5 eval6207n an evaluation board has been produced to help the evaluation of the device in powerdip package. it imple- ments a typical application with several added components. figure 53 shows the electrical schematic of the board; in the table below the part list is reported. cn1, cn2, cn3, cn4 2-poles connector jp1 3-pin jumper cn5 34-poles connector jp2, jp32-pin jumper c1 220nf/100v ceramic or polyester capacitor r1 100 w resistor c2 220nf/100v ceramic or polyester capacitor r2 3.17k w 0.6w resistor c3 100f/63v capacitor r3, r4 4.7k w resistor c4 10nf/100v ceramic capacitor r5, r16 20k w resistor c5 10f/16v capacitor r6, r7 100k w trimmer c6, c7 100nf capacitor r8, r17 2.2k w 0.4w resistor c8, c9 68nf capacitor r9 to r14 1 w 0.4w resistor c10, c11 820pf capacitor r18, r15 5k w trimmer d1, d2 1n4148 diode u1 l6205n d3 bzx79c5v1 5.1v zener diode u2 l6506 the evaluation board provides external connectors for the supply voltage, an external 5v reference for the logic inputs, four outputs for the motor and a 34-pin connector to control the main functions of the board through an external c board or the practispin tool. the practispin tool is composed of a graphic interface software running on a pc that connects with the hard- ware based on the st7 c, which contains an upgradeable firmware. this tool allows a fast and easy evaluation of the powerspin family devices, giving the ability of driving dc, bldc and stepper motors, depending on the target device. the practispin connected to the eval6207n can drive dc motors and inductive loads, allowing output voltage and current settings the pc-software also provides a power dissipation and thermal analysis section, intended to help a fast eval- uation of the device, package and dissipating copper area required by the users application, and to be a good starting point designing an application (from the power dissipation and thermal point of view). running the evaluation board in stand-alone mode, instead, r15 and r18 set the reference voltage separately for the two bridges, while r8, c8 and r17, c9 are low-pass filters to provide an external reference voltage by a pwm output of a c (see also the microstepping section). using external v ref inputs r5, r15, r16, r18 should be disconnected, unless the practispin st7 evaluation board is used. this board, in fact, is provided with an offset cancellation circuitry trimmable through a potentiometer (see practispin documentation). r6, c10 and r7, c11 are used to set the off-time of the two channels of the ic. closing jp2 and jp3 is recommended for safe over current protection. the 5v voltage for logic inputs and for references (v refa and v refb ) is obtained from r2, d3. depending on the supply voltage, the value of resistor r2 should be changed in order to ensure a correct biasing of d3. the jumper jp1 allows choosing the 5v voltage from the internal zener diode network or pin 11 of cn5 (for ex- ample an external c board can provide 5v to the evaluation board). also cn2 connector can be used to pro- vide an external 5v voltage to the board (in that case r2, d3 should be disconnected). cn2, or pin 1 of cn5, can also be used to provide a 5v voltage to external circuits (as, for example, the practispin st7 board). in this case the current that can be drawn form the board depends on the supply voltage and on r2 value. figure 54 to figure 56 show the component placement and the two layers layout of the l6207n evaluation board. a large gnd area has been used, to guarantee minimal noise and good power dissipation for the device.
AN1762 application note 50/53 figure 52. eval6207n. 5.5.1 important notes jp1 : close in int position for use with practispin st7 board c6, c7 : recommended change to 5.6 nf for safe overcurrent protection r3, r4 : recommended change to 100 k for safe overcurrent protection r15, r18 : set the maximum current obtainable through practispin (see practispin documentation) r2 : recommended change to adequate value (depending on supply voltage) to obtain 5v across d3 jp2, jp3 : close for safe overcurrent protection jp1 c6 c7 r3 r4 r15 r18 r2 jp2 jp3
51/53 AN1762 application note figure 53. eval6207n electrical schematic. +5v vref b sensea li mi tb vc cref li mi t a pullup pullup pullup +5v vref a vccref gn d senseb l6207 int2 adc_ref cw tinpb0 p2.1 a1in6 p8.1 toutao p2.2 int. tinpao p2.0 ocmpb1/icapb1 p4.3 touta1 p2.6 toutb1 p2.7 cw ocmpa0/icapa0 p3.2 a0in6 p7.6 ext. cw int0 ocmpb0 p3.3 ocmpa1 p4.2 r7 r5 c5 cn3 1 2 r12 r2 r4 r16 r6 r14 r18 c9 jp3 r15 jp2 r8 cn5 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 cn4 1 2 c11 r9 c3 d2 d3 c8 cn2 1 2 cn1 1 2 c2 r1 d1 jp1 1 3 2 c4 r3 r17 c1 c10 r13 r10 u1 in1a 1 in2a 2 sensea 3 rca/inh 4 out1a 5 gn d 6 gn d 7 ou t1b 8 rcb 9 senseb 10 in1b 11 in2b 12 vref b 13 enb 14 vboot 15 ou t2b 16 vsb 17 gn d 18 gn d 19 vsa 20 out2a 21 vcp 22 ena 23 vref a 24 c7 c6 r11 li mit_b in3 in4 li mi t_a li mi t_a in1 vref_a ena in2 in2 rca/inh in1 in3 ena vref b limi t_a in4 vrefa li mi t_b enb li mi t_b rca sense_b sense_a enb vref_b
AN1762 application note 52/53 figure 54. eval6207n component placement. figure 55. eval6207n top layer layout. power gnd (bulk capacitor) signal gnd
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com 53/53 AN1762 application note figure 56. eval6207n bottom layer layout. 6 references 1] d. arrigo, a. genova, t. hopkins, v. marano, a. novelli, "a new fully integrated stepper motor driver ic", proceedings of pcim 2001, september 2001, intertech communication. 2] h. sax, "stepper motor driving" (an235). 3] t. hopkins, "controlling voltage transients in full bridge driver applications" (an280). 4] p. casati and c. cognetti, "a new high power ic surface mount package family" (an668) short sense paths short sense paths signal gnd

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